Sasao T. (ed.) Logic Synthesis and Optimization

Springer, 1993. — 382.In July 1992, the International Symposium on Logic Synthesis and Microprocessor Architecture was held in Iizuka, Japan. The papers presented at the symposium were quite significant and we decided to publish the most outstanding of those concerned with Logic Synthesis and Optimization in textbook form for graduate students and young researchers.
There seem to be few textbooks of logic synthesis and optimization on the market. Thus, we would have no option but to turn to conference papers and journal papers to familiarize the students with the current status of research in the field, but we find most of them are just unsuitable for the students. Naturally, those papers are not education-oriented; they only offer a highly abstract description or explanation of the new ideas presented, mostly without any accompanying examples and illustrations, because of limited space.
To enhance their self-containedness, all the papers selected for publication here were reviewed by several people and were revised, in some cases extensively, and additional examples and illustrations, designed to increase the reader's understanding, were incorporated.
This book, which is organized into 16 chapters, deals with the following topics: Two-level minimization, Multi-level minimization, Application of binary decision diagrams, Delay optimization, Asynchronous circuits, Spectral method for logic design, Field programmable gate array design, EXOR logic synthesis, and Technology mapping.A New Exact Minimizer for Two-Level Logic Synthesis
A New Graph Based Prime Computation Technique
Logic Synthesers, the Transduction Method and Its Extension, Sylon
Network Optimization using Don't-Cares and Boolean Relations
Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning
A Partitioning Method for Area Optimization by Tree Analysis
A New Algorithm for 0-1 Programming Based on Binary Decision Diagrams
Delay Models and Exact Timing Analysis
Challenges to Dependable Asynchronous Processor Design
Efficient Spectral Techniques for Logic Synthesis
FPGA Design by Generalized Functional Decomposition
Logic Synthesis with EXOR Gates
AND-EXOR Expressions and Their Optimization
A Generation Method for Exorsum-of-Products Expressions using Shared Binary Decision Diagrams
A New Technology Mapping Method Based On Concurrent Factorization And Mapping
Gate Sizing for Cell-Based Designs