Scheffer L., Lavagno L., Martin G. (eds.) EDA for IC Implementation, Circuit Design, and Process Technology

Springer, 2006. — 602.Electronic Design Automation (EDA) is a spectacular success in the art of engineering. Over the last quarter of a century, improved tools have raised designers’ productivity by a factor of more than a thousand. Without EDA, Moore’s law would remain a useless curiosity. Not a single billion-transistor chip could be designed or debugged without these sophisticated tools, so without EDA we would have no laptops, cell phones, video games, or any of the other electronic devices we take for granted.
But spurred on by the ability to build bigger chips, EDA developers have largely kept pace, and these enormous chips can still be designed, debugged, and tested,-and in fact, with decreasing time to market. The story of EDA is much more complex than the progression of integrated circuit (IC) manufacturing, which is based on simple physical scaling of critical dimensions. Instead, EDA evolves by a series of paradigm shifts. Every chapter in this book, all 49 of them, was just a gleam in some expert’s eye just a few decades ago. Then it became a research topic, then an academic tool, and then the focus of a startup or two. Within a few years, it was supported by large commercial EDA vendors, and is now part of the conventional wisdom. Although users always complain that today’s tools are not quite adequate for today’s designs, the overall improvements in productivity have been remarkable. After all, in what other field do people complain of only a 21% compound annual growth in productivity, sustained over three decades, as did the International Technology Roadmap for Semiconductors in 1999?
And what is the future of EDA tools? As we look at the state of electronics and integrated circuit design in the 2005–2006 timeframe, we see that we may soon enter a major period of change in the discipline. The classical scaling approach to integrated circuits, spanning multiple orders of magnitude in the size of devices over the last 40_years, looks set to last only a few more generations or process nodes (though this has been argued many times in the past, and has invariably been proved to be too pessimistic a projection).
Conventional transistors and wiring may well be replaced by new nano and biologically-based technologies that we are currently only beginning to experiment with. This profound change will surely have a considerable impact on the tools and methodologies used to design integrated circuits. Should we be spending our efforts looking at CAD for these future technologies, or continue to improve the tools we currently use? Upon further consideration, it is clear that the current EDA approaches have a lot of life left in them. With at least a decade remaining in the evolution of current design approaches, and hundreds of thousands or millions of designs left that must either craft new ICs or use programmable versions of them, it is far too soon to forget about today’s EDA approaches. And even if the technology changes to radically new forms and structures, many of today’s EDA concepts will be reused and evolved for design into technologies well beyond the current scope and thinking.
The field of EDA for ICs has grown well beyond the point where any single individual can master it all, or even be aware of the progress on all fronts. Therefore, there is a pressing need to create a snapshot of this extremely broad and diverse subject. Students need a way of learning about the many disciplines and topics involved in the design tools in widespread use today. As design grows multi-disciplinary, electronics designers and EDA tool developers need to broaden their scope. The methods used in one subtopic may well have applicability to new topics as they arise. All of electronics design can utilize a comprehensive reference work in this field.
With this in mind, we invited many experts from across all the disciplines involved in EDA to contribute chapters summarizing and giving a comprehensive overview of their particular topic or field. As might be appreciated, such chapters represent a snapshot of the state of the art, written in 2004–2005. However, as surveys and overviews, they retain a lasting educational and reference value that will be useful to students and practitioners for many years to come.
With a large number of topics to cover, we decided to split the Handbook into two volumes. Volume 1 (/file/1876104/) covers system-level design, micro-architectural design, and verification and test. Volume 2 (/file/1876107/) covers the classical “RTL to GDS II” design flow, incorporating synthesis, placement and routing, along with related topics; analog and mixed-signal design, physical verification, analysis and extraction, and technology CAD topics. These roughly correspond to the classical “front-end/back-end” split in IC design, where the front end (or logical design) focuses on making sure that the design does the right thing, assuming it can be implemented, and the back-end (or physical design) concentrates on generating the detailed tooling required, while taking the logical function as given. Despite limitations, this split has persisted through the years — a complete and correct logical design, independent of implementation, remains an excellent handoff point between the two major portions of an IC design flow. Since IC designers and EDA developers often concentrate on one side of this logical/physical split, this seemed to be a good place to divide the book as well.
Volume II opens with an overview of the classical RTL to GDS II design flows, and then steps immediately into the logic synthesis aspect of “synthesis, place and route.” Power analysis and optimization methods recur at several stages in the flow. Recently, equivalence checking has increased the reliability and automation possible in the standard IC flows. We then see chapters on placement and routing and associated topics of static timing analysis and structured digital design. The standard back end flow relies on standard digital libraries and design databases, and must produce IC designs that fit well into packages and onto boards and hybrids. The relatively new emphasis on design closure knits many aspects of the flow together. Indeed, chapter 10, on design closure, is a good one to read right after Chapter 1, on design flows.
Before diving into the area of analog and mixed-signal design, the handbook looks at the special methods appropriate to FPGA design-this is a growing area for rapid IC design using underlying fixed but reprogrammable platforms. Then we turn to analog design, where we cover simulation methods, advanced modeling, and layout tools. Physical verification, analysis and extraction covers design rule checking, transformation of designs for manufacturability, analysis of power supply noise and other noise issues, and layout extraction. Finally, the handbook looks at process simulation and device modeling, and advanced parasitic extraction as aspects of technology CAD for ICs.
This handbook with its two constituent constitutes a valuable learning and reference work for everyone involved and interested in learning about electronic design and its associated tools and methods. We hope that all readers will find it of interest and a well-thumbed resource.Section I RTL to GDS-II, or Synthesis, Place, and Route
Design Flows
Logic Synthesis
Power Analysis and Optimization from Circuit to Register-Transfer Levels
Equivalence Checking
Digital Layout — Placement
Static Timing Analysis
Structured Digital Design
Routing
Exploring Challenges of Libraries for Electronic Design
Design Closure
Tools for Chip-Package Codesign
Design Databases
FPGA Synthesis and Physical Design
Section II Analog and Mixed-Signal Design
Simulation of Analog and RF Circuits and Systems
Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits
Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey
Section III Physical Verification
Design Rule Checking
Resolution Enhancement Techniques and Mask Data Preparation
Design for Manufacturability in the Nanometer Era
Design and Analysis of Power Supply Networks
Noise Considerations in Digital ICs
Layout Extraction
Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation
Section IV Technology CAD
Process Simulation
Device Modeling —From Physics to Electrical Parameter Extraction
High-Accuracy Parasitic Extraction